4th National FPGA Design Competition 2019
The 4th National FPGA Design Competition was organized by Digitronix Nepal,Logitronix Nepal and Kathford International College of Engineering and Management,Balkumari Lalitpur as the continuation of"FPGA Design Competition ",a yearly event.The theme of this competition was open. Enthusiast having any project on FPGA was eligible for the competition.While FPGA board implementation was not mandatory, so the simulation based design can also be completed and win.
Project Name : Design and an implementation of finite state machine using FPGA.
A system where particular inputs cause particular changes in state can be represented using finite state machine. Finite state machine can be used to model problem in many fields including mathematics, artificial intelligence, game and linguistics. A finite state machine (FSM) is a machine specified by a finite set of conditions of existence (called “states”) and a likewise finite set of transitions among the states triggered by events. A sequence detection is an implementation of finite state machine (FSM).
A sequential logic unit which takes an input and a current state also produces an output and a new state. It is composed of a combinational logic unit and flipflops placed in such a way as to maintain state information. Finite automata may have output corresponding to each transition. There are two types of finite state machine that generate output.
Mealy Machine
It is an FSM whose output depends on the present state as well as the present input. It has fewer state. It reacts faster to input. They generally react in the same block.
It is an FSM whose output depends on the present state as well as the present input. It has fewer state. It reacts faster to input. They generally react in the same block.
Moore Machine
It is an FSM whose output depend on only the present state. It has more states. More logic is required to decode the outputs resulting in more circuit delays. They generally react one clock cycle later.
Documentation of Project: Download
It is an FSM whose output depend on only the present state. It has more states. More logic is required to decode the outputs resulting in more circuit delays. They generally react one clock cycle later.
Documentation of Project: Download
Participants:
No comments:
Post a Comment